Učni načrt predmeta

Predmet:
Vgradni sistemi
Course:
Embedded Systems
Študijski program in stopnja /
Study programme and level
Študijska smer /
Study field
Letnik /
Academic year
Semester /
Semester
Informacijske in komunikacijske tehnologije, 2. stopnja Računalniške strukture in sistemi 1 2
Information and Communication Technologies, 2nd cycle Computer Structures and Systems 1 2
Vrsta predmeta / Course type
Izbirni / Elective
Univerzitetna koda predmeta / University course code:
IKT2-694
Predavanja
Lectures
Seminar
Seminar
Vaje
Tutorial
Klinične vaje
work
Druge oblike
študija
Samost. delo
Individ. work
ECTS
30 30 30 210 10

*Navedena porazdelitev ur velja, če je vpisanih vsaj 15 študentov. Drugače se obseg izvedbe kontaktnih ur sorazmerno zmanjša in prenese v samostojno delo. / This distribution of hours is valid if at least 15 students are enrolled. Otherwise the contact hours are linearly reduced and transfered to individual work.

Nosilec predmeta / Course leader:
doc. dr. Anton Biasizzo
Sodelavci / Lecturers:
Jeziki / Languages:
Predavanja / Lectures:
slovenščina, angleščina / Slovenian, English
Vaje / Tutorial:
Pogoji za vključitev v delo oz. za opravljanje študijskih obveznosti:
Prerequisits:
Vsebina:
Content (Syllabus outline):
Temeljna literatura in viri / Readings:
Cilji in kompetence:
Objectives and competences:
Predvideni študijski rezultati:
Intendeded learning outcomes:
Metode poučevanja in učenja:
Learning and teaching methods:
Načini ocenjevanja:
Delež v % / Weight in %
Assesment:
Seminarska naloga
50 %
Seminar work
Ustni zagovor seminarske naloge
50 %
Oral defense of seminar work
Reference nosilca / Lecturer's references:
1. U. Legat, A. Biasizzo, and F. Novak, “SEU recovery mechanism for SRAM-based FPGAs”,IEEE trans. on nuclear science, vol. 59, no 5, pp. 2562-2571, 2012.
2. A. Biasizzo and F. Novak, “Hardware accelerated compression of LIDAR data using FPGA devices”, Sensors, vol. 13, no. 5, pp. 6405-6422, 2013.
3. A. Biasizzo, “ On-line testing and recovery of systems with dynamic partial reconfiguration = Sprotno preiskušanje in popravljanje sistemov z dinamično delno rekonfiguracijo”, Informacije MIDEM, vol. 43, no. 4, pp. 259-266, 2013.
4. A. Biasizzo, F. Novak, and P. Korošec, “A multi-alphabet arithmetic coding hardware implementation for small FPGA devices”, Journal of electrical engineering, vol. 64, no. 1, pp 44-49, 2013.
5. A. Biasizzo and F. Novak, “Security problems of scan design and accompanying measures”, Journal of electrical engineering, vol. 67, no. 3, pp 192-198, 2016.